The present invention relates to a differential amplifier circuit (DIFF-AMP circuit) having an improving circuit to shorten a circuit recovery time of the DIFF-AMP circuit when the amplitude of an input signal of the DIFF-AMP circuit exceeds a linear operating region.
Generally, when the amplitude of an input signal to a DIFF-AMP circuit is too large, the DIFF-AMP circuit is driven into a saturation region of operation. An initial state of the DIFF-AMP circuit is thereby changed to a second state (saturation state) in which the DIFF-AMP circuit cannot be used normally to produce a normal output having a sufficient amplitude until the DIFF-AMP returns from the second state back to the initial state. The time in which the DIFF-AMP circuit returns from the second state back to the initial state will be called circuit recovery time hereinafter. The circuit recovery time depends on an amplitude of the input signal; that is, the circuit recovery time is lengthened when the input amplitude is large.
Therefore, when a DIFF-AMP circuit is used in an integrated circuit (IC) device such as an operational amplifier or a comparator and the amplitude of a differential input signal to the DIFF-AMP circuit exceeds a liner operating region of the DIFF-AMP circuit, a circuit recovery time of the DIFF-AMP circuit is lengthened and it is driven into the second state. This second state continues until the recovery time is over even though an amplitude of a differential input signal successively fed to the DIFF-AMP circuit is so sufficiently small that the DIFF-AMP circuit would otherwise operate within a normal linear region.
FIG. 1 shows an operational amplifier including a conventional DIFF-AMP circuit. In FIG. 1, differential input signals S1 and S2 are fed to the gates of n channel (n-ch) type metal oxide semiconductor (MOS) transistors T1 and T2 through the input terminals -In and +In respectively; wherein, the MOS transistors T1 and T2 form a differential input stage and the input signals S1 and S2 are an inverting input signal and a non-inverting input signal respectively. The drain electrodes of the MOS transistors T1 and T2 are directly connected to the drain electrodes of p channel (p-ch) transistors T3 and T4 through nodes N1 and N2 respectively. The transistors T3 and T4 are loads of the transistors T1 and T2 respectively and form a current mirror circuit. The node N2 is connected to the gate of a p-ch MOS transistor T5 which is an output stage of the operational amplifier. Reference symbols J1 and J2 are constant current sources respectively, +V and -V are a plus power supply voltage and a minus power supply voltage respectively and OUT is an output terminal of the operational amplifier.
In FIG. 1, when the voltage difference between differential input signals S1 and S2 increases a T1 current which flows through the transistor T1 increases. A current ratio, which will be called a first current ratio hereinafter, of T1 current to a T2 current which flows through the transistor T2 increases, because the source electrodes of transistors T1 and T2 are connected in common with the constant current source J1. Then, a current ratio of a T3 current, which flows through the transistor T3, to a T4 current, which flows through the transistor T4, must be equal to the first current ratio because transistors T3 and T4 are the loads of transistors T1 and T2 respectively. However, since the transistors T3 and T4 form the current mirror circuit, the T4 current tends to be equal to the T3 current. Therefore, a potential at the node N2 rises up to almost the power supply voltage +V, so that the transistor T5 is forced to be completely cut off.
After the input differential signals S1 and S2 having the large voltage difference are over, the risen potential at the gate of the transistor T5 decreases. However, this decrease takes time (recovery time) until a current starts to flow through the transistor T5 because it takes a time to allow the charged stray capacitance around the node 2 and the gate of the transistor T5 due to the risen potential to discharge. The recovery time continues even though succeeding differential input signals S1 and S2 have normal amplitude, such that a voltage difference between the succeeding differential input signals is in the operating region of the operational amplifier. The differential input signals S1 and S2 are pulse signals having a repetition rate. Therefore, if the recovery time is lengthened, the repetition rate must be decreased resulting in a decrease of operational speed of the operational amplifier. This has been a problem (a first problem) in DIFF-AMP circuits.
The first problem has been solved by applying diode clampers to the DIFF-AMP circuit. This has been disclosed in a technical paper "A Two Chip PCM Voice CODEC with Filters", by Y. A. HAQUE et al, in the IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979.
FIG. 2 shows a circuit diagram of a DIFF-AMP circuit including diode clampers. This circuit is called "a diode clamped preamplifier" according to the IEEE paper and the circuit diagram is a part of a circuit diagram (FIG. 5 in the paper) for "a comparator" which is discussed in paragraph D on page 964 of the paper. The paper says that "the output of a non diode clamped differential stage undergoes large voltage excursions and under sufficient input voltage it drives the output devices out of the saturation region of operation. Therefore, in switching from one state to another, the comparator initially starts with a low gain resulting in a slow response time. Diode clamps on the output nodes (node 2) limits the voltage excursion of the output nodes and thus improves the transient response."
In FIG. 2, transistors Q14 and Q15 correspond to the transistors T1 and T2 of FIG. 1; transistors Q16 and Q17 correspond to the transistors T3 and T4 of FIG. 1 and form a current mirror circuit; nodes 1 and 2 correspond to the nodes N1 and N2 of FIG. 1 transistor Q13 corresponds to the constant current source J1 in FIG. 1. A combination of transistors Q18 and Q19, and that of Q20 and Q21 respectively form source followers each corresponding to the output stage T5 in FIG. 1. When the transistors Q14 and Q15 receive differential input signals "(+)" and "(-)" respectively and a current ratio of a current flowing through the transistor Q14 to a current flowing through the transistor Q15 increases, the potential at the node 2 tends to rise up to a power supply voltage +V. However, since a diode D2 is connected between the nodes 1 and 2, the potential at the node 2 can be kept to a forward voltage drop, which is approximately 0.6 V to 0.8 V higher than the potential at the node 1. A diode D1 acts the same as the diode D2 when a current ratio of the current flowing through the transistor Q15 to the current flowing through the transistor Q14 increases. Because of thus using the diodes D1 and D2 to the DIFF-AMP circuit, the voltage excursion of the nodes 1 and 2 can be limited and the transient response in the DIFF-AMP circuit can be improved.
However, the circuit still has a problem (a second problem) as follows:
(1) generally, diodes are hard to fabricate with complementary MOS (CMOS) transistors in an IC device because of a latch-up problem;
(2) therefore, if an IC device including the CMOS transistors is forced to be fabricated with diodes, the reliability of the IC device would be reduced and the cost of the IC device would be increased; and
(3) since a forward voltage drop of each clamping diode D1 or D2 is fixed, for example, from 0.6 V to 0.8 V in a case of a silicon diode, the voltages at the output nodes 1 and 2 of the DIFF-AMP circuit become uncontrollable, which causes the following problems:
first, the designing freedom of an IC device including the DIFF-AMP circuit having the clamping diodes is restricted; and
second, an operation speed of the DIFF-AMP circuit cannot be expected to be high, because, generally, a threshold voltage (V.sub.th) of an output stage of a DIFF-AMP circuit is set low for increasing the operation speed of the DIFF-AMP circuit; however, the V.sub.th cannot be decreased so low as long as the clamping diode (D2) is used in the DIFF-AMP circuit, because the V.sub.th must be always set above the summation of the diode (D2) forward voltage drop and the voltage at the node 1 for making the clamping function of the diode (D2) occur. In other words, the V.sub.th cannot be reduced below the summed voltage of the diode forward voltage drop and the voltage at the node 1.